The present invention is directed to a digital phase-locked loop (DPLL), and more particularly, to an auto-adaptive DPLL for large frequency multiplication factors.
Existing designs for a phase locked-loop use either an analog (i.e., APLL) architecture or a DPLL architecture. An APLL requires custom design and careful tuning of all analog components in the design in order to perform its function accurately. Two crucial components of an APLL are a voltage-controlled oscillator (VCO) and a low-pass filter. It is difficult for an APLL to simultaneously achieve highly stable operation with a fast locking time because these two design requirements conflict with each other. The low-pass filter requires that the bandwidth be narrow enough to reject any high-frequency noise, but also be wide enough to meet the desired locking time requirements at a desired generated clock frequency. For applications that operate over a wide range of frequencies, programmable tuning parameters are provided in the APLL to control the functioning of the design. Requirements for tuning the APLL parameters make the overall design more complex and costly to produce, and make each application more complicated to implement.
Existing DPLL designs typically perform frequency synthesis using a numerically controlled oscillator (NCO). The NCO relies on an accurately controlled delay line and an external crystal reference oscillator. Some implementations of existing DPLL designs can also use an analog to digital (i.e., A/D) converter for generating a sinusoidal clock waveform. Therefore, even a conventional DPLL may have a significant number of analog components associated with its architecture, which requires a similar design effort as required for the components of an APLL.
The present invention is directed to an auto-adaptive DPLL for large frequency multiplication factors and a method for producing a generated clock frequency output that avoids one or more problems resulting from the limitations and disadvantages of the prior art APLL and DPLL designs.
The auto-adaptive DPLL generates a clock frequency based on an input reference clock frequency, the generated clock frequency being a large integer multiple (e.g., greater than 100) of the input reference clock frequency.
A typical application for the auto-adaptive DPLL is in a high definition television (HDTV) or a standard definition television (SDTV) pixel clock generator, which is based on a horizontal synchronization signal. The reference frequency is in the range of 10 kHz to 100 kHz with the generated pixel clock frequency in the range from about 20 MHz to 200 MHz. The frequency multiplication factor in this application is typically in the range from about 858 to 2200, but the factor and range may be different for other applications. Some of the requirements for the pixel clock include a very highly stable operation and a very fast locking time over a wide range of reference frequencies and frequency multiplication factors, as defined by various HDTV and SDTV standards.